The Hitachi SH-7604 Hardware Manual defines the IE bit (bit #2) in CHCR register (§9.2.4) as :
(typo theirs)Interrupt Enable Bit (IE): Determines whether or not to request a CPU interrupt at the end of a DMA transfer. When the IE bit is set to 1, an interrupt (DEI) request is setnt to the CPU when the TE bit is set.
Then, the VCRDMA register (§9.2.5) :
Finally, regarding the DMA Transfer Flow (§9.3.1)When a transfer-end interrupt occurs, exception handling and interrupt control fetch the vector number and control is transferred to the specified interrupt handling routine.
So, I have tried to raise a DEI at the end of a DMA (initiated by the 32X, with the DREQ circuitry).If the IE bit in CHCR is set to 1 at this time (end of transfer), a DEI interrupt is sent to the CPU.
I've set the IE bit,
I have defined a vector in the VCRDMA,
defined a function address in the VBR,
then set up CHRC as $44E5 instead of $44E1.
But it failed.
So, my questions are,
- is DEI implemented in any emulator ?
- has anyone ever tested it on real hardware ?
The idea would be to purge the cache lines of the uploaded data as soon as the DMA is complete.
For now, I bypass this with polling : as soon as the 32x is asked for a DMA, I enable HINT. When I HINT, I check CHCR. If CHCR.TE is set, the DMA is finished and I can purge the cache.
I have searched some commercial ROMs (VR, Kolibri, Knuckles), but none of them seem to use the DREQ :/